What is CUSPARC ?

First, What is SPARC?

SPARC is a CPU instruction set architecture (ISA), derived from a reduced instruction set computer (RISC). It allows for a spectrum of different system implementations for many applications (scientific/engineering, programming, real-time, and commercial). SPARC was designed as a target for optimizing compilers and easily pipelined hardware implementations. For languages such as C++, where object-oriented programming is dominant, register windows, supported by SPARC, result in greater reduction of instructions executed, giving less Clock Per Instruction (CPI).

CUSPARC

CUSPARC is a 32bit, pipelined processor that is completely designed in Cairo University conforming to SPARC v8 standard for embedded systems’ processors. CUSPARC started as a graduation project in 2004, and still going on as a graduation project till 2010, under the supervision of Prof. Serag El-Din Habib (Electronics & Communications Dept.). The design was at first targeting FPGA and was modified by 2007 ASIC team to be implemented using the 0.35u Austrian MicroSystems (AMS) technology.

In 2008, there was a breakthrough in CUSPARC history when this team made a new version of the processor (CUSPARC v.2). The new version was made targeting ASIC design for better performance and less area than the first one.

So, until now this version is the last one of CUSPARC, and it's been fabricated through an MEP (MOSIS Educational Program). Testing is being carried out, and results will be posted on this blog.

Find the comparison between the two versions of CUSPARC, and LEON 1 processor from Gaisler Research. (The CUSPARC v2 specs are based on 0.35u technology design).